Your program's memory addresses are not real. On any modern computer, the address your code supplies is a virtual address, translated to a physical location by the Memory Management Unit using page tables, cached by a Translation Lookaside Buffer, and potentially backed by disk swap space rather than RAM. The data you read may live in L1, L2, or L3 cache, each with different latencies, before physical DRAM is ever touched. On NUMA systems, which processor node owns that RAM determines whether your read is fast or crosses an interconnect entirely.
The 64-byte cache line is the detail most programmers miss. CPUs do not fetch individual bytes. They fetch 64-byte blocks, which means two threads writing to separate variables that share a cache line will hammer the MESI coherence protocol invalidating each other's copies. Sequential memory access outperforms random access not by accident but because hardware prefetchers read ahead in 64-byte chunks. The piece is worth reading in full specifically for how it walks through MESI states, TLB misses, and why a page fault can silently cost you hundreds of thousands of cycles.
The article ends where the hardware industry is heading: CXL interconnects, chiplet architectures, and heterogeneous memory pools are making the memory topology problem worse, not simpler. The 4 KB page and the flat address space abstraction are holding. The physics underneath them are not.
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